The ChipList, by Adrian Offerman; The Processor Portal

Processor Selector

View: show / edit

bookmark bookmark site
bookmark permalink
Processors » Technology »

AMD: No Core Wars

Entering the era of heterogenous multi-cores

September 11, 2007 - There will be no core wars, Guiseppe Amato, director, technical marketing, AMD EMEA, emphasized at the introduction of the Quad-Core Opteron Barcelona processors today. By the end of the decade, homogenous multi-cores will become increasingly inadequate. In the coming era of what AMD calls Accelerated Computing, heterogenous multi-cores will go mainstream.

First, this will take shape in specific coprocessors fitting AMD's multi-processor sockets (socket-compatible accelerators), built on the motherboard and connected to the chipset (e.g. Stream) or to the CPU directly (via HyperTransport Expansion, HTX slots). This is what AMD calls the Torrenza platform.

These Direct Connect Accelerators can be I/O interfaces or coprocessors for specific workloads and tasks. Java, XML, vector FP computing, and media processing, to name a few. When not being used, these accelerators drop to low-power states.

The Stream processor is a GPGPU (General-Purpose GPU). It can be used for imaging, video, and data intensive processing or HPC in general. According to AMD, using Stream results in twenty times the performance for specific workloads, compared to running the same task on a Dual-Core processor.

Continuum of Accelerated Solutions. [AMD]

Accelerated Processing Units

Later, domain specific accelerators will be integrated in the processor, either in the same package (Multi-Chip Module, MCM) or on the die itself (chip-level integration). This is what AMD calls Fusion.

Processors will exist of combinations of both Central Processing Units (CPUs) and specific xPUs, brought together in Accelerated Processing Units (APUs). The first implementation will be a combination of a next generation Bulldozer core and a DirectX GPU (Graphics Processing Unit), together with a Unified Video Decoder (UVD), a memory controller, and PCIe.

Page viewed 4754 times since Sun 1 Mar 2009, 0:00.