The ChipList, by Adrian Offerman; The Processor Portal

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AMD Sempron processor (Paris, revision CG)

Identification


Model name: Sempron.
Code name: Paris, revision CG.
Family name: Cities.
Supplier: AMD.
Component class: CPU.

Generation


Generation: K8.

Compatibility


Multimedia instruction sets: MMX, Enhanced 3DNow!, SSE, SSE2.

Cache


L1 cache: 64 kbyte instruction cache, 64 kbyte data cache (Harvard architecture).
L2 cache: 256 kbyte (other 256 kbyte disfunctional/disabled) or 128 kbyte (other 384 kbyte disfunctional/disabled).

Architecture


64 bit, 200 MHz, DDR memory controller: max. 4 x 512 Mbyte = 2 Gbyte (2 x 1 Gbyte double-sided PC3200 memory module).

800 MHz HyperTransport bus.

Memory protection: NX bit (Enhanced Virus Protection, EVP).

Multiplier


Clock speed


Clock speed Model Cache Multiplier Introduction Order part numbers
200 MHz / 1.80 GHz AMD Sempron 3000+ CPU 128 kbyte L2 9 February 2005 OEM: SDA3000AIP2AX,
PIB: SDA3000AXBOX
200 MHz / 1.80 GHz AMD Sempron 3100+ CPU 256 kbyte L2 9 July 2004 OEM: SDA3100AIP3AX,
PIB: SDA3100AXBOX

Physics


Voltage: 1.40 V.
Power dissipation: 62 W TDP.

Temperature: max. 70 °C.

Manufacturing process: 0.13 micron.

Number of transistors: 68.5 million.

Die size: 144 mm2.

Packaging: Socket 754.

Step level


Text:

Step levels: CG.

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