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0.2.8  Intel Core 2 Duo T9xxx series mobile processor (Penryn)


Model name: Core 2 Duo T9xxx series.
Code name: Penryn.
Supplier: Intel.
Component class: CPU.


Generation: Core 2.


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 6 Mbyte.


100-200 MHz QDR bus (Dynamic Front-Side Bus Frequency Switching).

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).


Dual-core technology.

Intel Dynamic Acceleration (IDA): while running extended serial code, one core can temporary run at a higher frequency while the other is turned off, so the total power dissipation stays within the operating limits.


Power management

Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed

Clock speed Model Multiplier Introduction Order part numbers
200/2500 MHz Intel Core 2 Duo T9300 CPU 12.5 January 2008 OEM (BGA): EC80576GG0606M,
OEM (PGA): FF80576GG0606M,
PIB (PGA): BX80576T9300
200/2600 MHz Intel Core 2 Duo T9500 CPU 13 January 2008 OEM (BGA): EC80576GG0646M,
OEM (PGA): FF80576GG0646M



  • s-spec SLAPV, SLAPW: (1.00-1.250 V),
  • others: (1.062-1.150 V).

Power dissipation: 35 W TDP.

Temperature: 0-100 °C.

Manufacturing process: 45 nm (P1266).

Number of transistors: 410 million.

Die size: 110 mm2.

Packaging: Socket P.

System management

Remote management: Intel Active Management (iAMT2).


Extended family Extended model Type Family Model Stepping Description
0x0 0x1 0x0 0x6 0x7 0x6 stepping C0

Step level


Step levels: C0.

S-Spec / Stepping code

Model Code Stepping
Intel Core 2 Duo T9300 CPU SLAPV C0
Intel Core 2 Duo T9500 CPU SLAPW C0
Intel Core 2 Duo T9300 CPU SLAQG C0
Intel Core 2 Duo T9500 CPU SLAQH C0
Intel Core 2 Duo T9500 CPU SLAYY C0

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