Intel Dual-Core Xeon MP E7200 series processor (Tigerton-DC)

Identification

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Model name: Dual-Core Xeon MP E7200 series.
Code name: Tigerton-DC.
Supplier: Intel.
Component class: CPU.

Generation

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Generation: Core 2.

Compatibility

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64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache

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L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Two-by-two shared L2 cache: (2x) 4 Mbyte (one per available core).

Architecture

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266 MHz QDR Dedicated High Speed Interconnect (DHSI): connecting the CPU socket directly to the chipset on the motherboard (Multi Independent Bus, MIB); main memory talks to the chipset, not directly to the processor chips.

Memory protection: XD bit.

Protected program execution environment: LaGrande Technology (LT).

Virtualization Technology (VT, Vanderpool), with:

• VT FlexMigration: enabling future processor generations to impersonate a previous generation, allowing virtual machines (vms) to live migrate to another processor generation without disturbing the architectural image that applications are having.

Multi-processing

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Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).
Only one core per die available; other core disfunctional/disabled.

Symmetric Multi-Processing (SMP): supported through chipset.

Multiplier

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Power management

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Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed

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Physics

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Voltage: 1.200-1.325 V.
Power dissipation: 80 W TDP.

Manufacturing process: 65 nm (P1264).

Number of transistors: (2x) 291 million.

Die size: (2x) 143 mm².

Packaging: Socket 604.

Thermal management

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Thermal Monitor: TM1, TM2.

System management

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Remote management: Intel Active Management (iAMT2).

CPUID32

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Step level

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Text:

Step levels: G0.

S-Spec / Stepping code

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