HP Itanium 2 mx2 processor module (Hondo)

Dual-Processor version of Intel Itanium 2 Madison processor (Dual-Chip Module, DCM).
Drop-in replacement for Pentium 2 processors.

Identification

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Model name: Itanium 2 mx2.
Code name: Hondo.
Family name: Itanium Processor Family (IPF).
Supplier: HP.
Component class: CPU.

Generation

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Generation: Itanium 2.

Compatibility

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Bi-endian memory access.

Processor virtualization.

IA-32 compatibility mode: IA-32 System Environment.
16 bit Real Mode, 16 bit VM86, 16/32 bit Protected Mode, memory segmentation.
Multimedia instruction sets: MMX, SSE.

PA-RISC supported through Aries emulator.

Extensible Firmware Interface (EFI).
System Abstraction Layer (SAL).
Processor Abstraction Layer (PAL).

Cache

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On-die L1 cache (Harvard architecture):

• (2x) 16 kbyte instruction cache,
• (2x) 16 kbyte data cache.

On-die, unified L2 cache: (2x) 256 kbyte.

On-die, unified L3 cache: (2x) 4 Mbyte.

L4 cache: 32 Mbyte, shared, apart in package, connected through Front Side Bus (FSB).

Architecture

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Virtual address space: 64 bit, no segmentation.
Multiple Address Space (MAS): each process has its own unique Virtual Region (flat linear address space).
8 61 bit Virtual Regions, 2²⁴ Virtual Address Spaces of 2⁶¹ bits.
4 kbyte - 4 Gbyte pages.

Physical address space: 63 bit.
Up to 50 bits supported in page tables.

Write Coalescing (WC): streams of non-cachable writes can be combined into a single bus write transaction.
WC Buffer (WCB): two-entry, 128 byte.

Enhanced Machine Check Architecture (EMCA): parity and ECC (Error-Correcting Code) on all major address and data busses.

50 bit address bus.
Physical addressing:

• 32 bit: 0-4 Gbyte,
• 36 bit: 4-64 Gbyte,
• 44 bit: 64 Gbyte - 16 Tbyte.

Virtual addressing: 54 bit.
Page sizes: 4 kbyte - 4 Gbyte.

200 MHz DDR bus (McKinley bus, Scalability Port): 128 bit data.

Multi-processing

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SMP (Symmetric Multi-Processing): glueless up to two processor packages only.

Multiplier

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Multiplier: 2/11.

Power management

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Power and performance management: P-states.

Clock speed

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Physics

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Manufacturing process: 130 nm.

Number of transistors: (2x) 410 million.

Die size: (2x) 374 mm².

Packaging: PAC611.

Thermal management

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Thermal management:

• Thermal Alert,
• Enhanced Thermal Management (ETM),
• Thermal Trip.

System management

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System management: System Management Bus (SMBus).

Step level

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Text:

Step levels: B1.

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