Added with 80486 Instruction Set Architecture (ISA)

Instructions added with the 80486 processors:

• BSWAP
  Byte Swap
• CMPXCHG
  Compare and Exchange
• CPUID (introduced in SL Enhanced models)
  CPU Identification
• INVD
  Invalidate Internal Caches
• INVLPG
  Invalidate TLB Entry
• RSM (introduced in SL Enhanced models)
  Resume from System Management Mode
• WBINVD
  Write Back and Invalidate Cache
• XADD
  Exchange and Add