SSE Instruction Set Architecture (ISA) Extension

SSE instructions added with the Pentium III processors:

• MASKMOVQ
  Store Selected Bytes of Quadword
• MOVNTPS
  Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint
• MOVNTQ
  Store of Quadword Using Non-Temporal Hint
• PREFETCHh (PREFETCH0, PREFETCH1, PREFETCH2, PREFETCHNTA)
  Prefetch Data Into Caches
• SFENCE
  Store Fence

SSE Floating-Point (FP) instructions added with the Pentium III processors:

• FXRSTOR
  Restore x87 FPU, MMX, XMM, and MXCSR State
• FXSAVE
  Save x87 FPU, MMX Technology, SSE, and SSE2 State

SSE SIMD integer instructions added with the Pentium III processors:

• PAVGB/PAVGW
  Average Packed Integers
• PEXTRW
  Extract Word
• PINSRW
  Insert Word
• PMAXSW
  Maximum of Packed Signed Word Integers
• PMAXUB
  Maximum of Packed Unsigned Byte Integers
• PMINSW
  Minimum of Packed Signed Word Integers
• PMINUB
  Minimum of Packed Unsigned Byte Integers
• PMOVMSKB
  Move Byte Mask
• PMULHUW
  Multiply Packed Unsigned Integers and Store High Result
• PSADBW
  Compute Sum of Absolute Differences
• PSHUFW
  Shuffle Packed Words

SSE SIMD Floating-Point (FP) instructions added with the Pentium III processors:

• ADDPS
  Add Packed Single-Precision Floating-Point Values
• ADDSS
  Add Scalar Single-Precision Floating-Point Values
• ANDPS
  Bitwise Logical AND of Packed Single-Precision Floating-Point Values
• ANDNPS
  Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values
• CMPPS
  Compare Packed Single-Precision Floating-Point Values
• CMPSS
  Compare Scalar Single-Precision Floating-Point Values
• COMISS
  Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS
• CVTPI2PS
  Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
• CVTPS2PI
  Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
• CVTSI2SS
  Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
• CVTSS2SI
  Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer
• CVTTPS2PI
  Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
• CVTTSS2SI
  Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
• DIVPS
  Divide Packed Single-Precision Floating-Point Values
• DIVSS
  Divide Scalar Single-Precision Floating-Point Values
• LDMXCSR
  Load MXCSR Register
• MAXPS
  Return Maximum Packed Single-Precision Floating-Point Values
• MAXSS
  Return Maximum Scalar Single-Precision Floating-Point Value
• MINPS
  Return Minimum Packed Single-Precision Floating-Point Values
• MINSS
  Return Minimum Scalar Single-Precision Floating-Point Value
• MOVAPS
  Move Aligned Packed Single-Precision Floating-Point Values
• MOVHLPS
  Move Packed Single-Precision Floating-Point Values High to Low
• MOVHPS
  Move High Packed Single-Precision Floating-Point Values
• MOVLHPS
  Move Packed Single-Precision Floating-Point Values Low to High
• MOVLPS
  Move Low Packed Single-Precision Floating-Point Values
• MOVMSKPS
  Extract Packed Single-Precision Floating-Point Sign Mask
• MOVSS
  Move Scalar Single-Precision Floating-Point Values
• MOVUPS
  Move Unaligned Packed Single-Precision Floating-Point Values
• MULPS
  Multiply Packed Single-Precision Floating-Point Values
• MULSS
  Multiply Scalar Single-Precision Floating-Point Values
• ORPS
  Bitwise Logical OR of Single-Precision Floating-Point Values
• RCPPS
  Compute Reciprocals of Packed Single-Precision Floating-Point Values
• RCPSS
  Compute Reciprocal of Scalar Single-Precision Floating-Point Values
• RSQRTPS
  Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values
• RSQRTSS
  Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value
• SHUFPS
  Shuffle Packed Single-Precision Floating-Point Values
• SQRTPS
  Compute Square Roots of Packed Single-Precision Floating-Point Values
• SQRTSS
  Compute Square Root of Scalar Single-Precision Floating-Point Value
• STMXCSR
  Store MXCSR Register State
• SUBPS
  Subtract Packed Single-Precision Floating-Point Values
• SUBSS
  Subtract Scalar Single-Precision Floating-Point Values
• UCOMISS
  Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS
• UNPCKHPS
  Unpack and Interleave High Packed Single-Precision Floating-Point Values
• UNPCKLPS
  Unpack and Interleave Low Packed Single-Precision Floating-Point Values
• XORPS
  Bitwise Logical XOR for Single-Precision Floating-Point Values