The ChipList, by Adrian Offerman; The Processor Portal
bookmark bookmark site
del.icio.us save to del.icio.us
bookmark permalink
Digg This Story

SSE5 Instruction Set Architecture (ISA) Extension

128 bit instructions to be added with the Bulldozer processors:

  • COMPD
    Compare Vector Double-Precision Floating-Point
  • COMPS
    Compare Vector Single-Precision Floating-Point
  • COMSD
    Compare Scalar Double-Precision Floating-Point
  • COMSS
    Compare Scalar Single-Precision Floating-Point
  • CVTPH2PS
    Convert 16-Bit Floating-Point to Single-Precision Floating-Point
  • CVTPS2PH
    Convert Single-Precision Floating-Point to 16-Bit Floating-Point
  • FMADDPD
    Multiply and Add Packed Double-Precision Floating-Point
  • FMADDPS
    Multiply and Add Packed Single-Precision Floating-Point
  • FMADDSD
    Multiply and Accumulate Scalar Double-Precision Floating-Point
  • FMADDSS
    Multiply and Add Scalar Single-Precision Floating-Point
  • FMSUBPD
    Multiply and Subtract Packed Double-Precision Floating-Point
  • FMSUBPS
    Multiply and Subtract Packed Single-Precision Floating-Point
  • FMSUBSD
    Multiply and Subtract Scalar Double-Precision Floating-Point
  • FMSUBSS
    Multiply and Subtract Scalar Single-Precision Floating-Point
  • FNMADDPD
    Negative Multiply and Add Packed Double-Precision Floating-Point
  • FNMADDPS
    Negative Multiply and Add Packed Single-Precision Floating-Point
  • FNMADDSD
    Negate Multiply and Add Scalar Double-Precision Floating-Point
  • FNMADDSS
    Negative Multiply and Add Scalar Single-Precision Floating-Point
  • FNMSUBPD
    Negative Multiply and Subtract Packed Double-Precision Floating-Point
  • FNMSUBPS
    Negative Multiply and Subtract Packed Single-Precision Floating-Point
  • FNMSUBSD
    Negative Multiply and Subtract Scalar Double-Precision Floating-Point
  • FNMSUBSS
    Negative Multiply and Subtract Scalar Single-Precision Floating-Point
  • FRCZPD
    Extract Fraction Packed Double-Precision Floating-Point
  • FRCZPS
    Extract Fraction Packed Single-Precision Floating-Point
  • FRCZSD
    Extract Fraction Scalar Double-Precision Floating-Point
  • FRCZSS
    Extract Fraction Scalar Single-Precision Floating Point
  • PCMOV
    Vector Conditional Moves
  • PCOMB
    Compare Vector Signed Bytes
  • PCOMD
    Compare Vector Signed Doublewords
  • PCOMQ
    Compare Vector Signed Quadwords
  • PCOMUB
    Compare Vector Unsigned Bytes
  • PCOMUD
    Compare Vector Unsigned Doublewords
  • PCOMUQ
    Compare Vector Unsigned Quadwords
  • PCOMUW
    Compare Vector Unsigned Words
  • PCOMW
    Compare Vector Signed Words
  • PERMPD
    Permute Double-Precision Floating-Point
  • PERMPS
    Permute and Modify Single-Precision Floating Point
  • PHADDBD
    Packed Horizontal Add Signed Byte to Signed Doubleword
  • PHADDBQ
    Packed Horizontal Add Signed Byte to Signed Quadword
  • PHADDBW
    Packed Horizontal Add Signed Byte to Signed Word
  • PHADDDQ
    Packed Horizontal Add Signed Doubleword to Signed Quadword
  • PHADDUBD
    Packed Horizontal Add Unsigned Byte to Doubleword
  • PHADDUBQ
    Packed Horizontal Add Unsigned Byte to Quadword
  • PHADDUBW
    Packed Horizontal Add Unsigned Byte to Word
  • PHADDUDQ
    Packed Horizontal Add Unsigned Doubleword to Quadword
  • PHADDUWD
    Packed Horizontal Add Unsigned Word to Doubleword
  • PHADDUWQ
    Packed Horizontal Add Unsigned Word to Quadword
  • PHADDWD
    Packed Horizontal Add Signed Word to Signed Doubleword
  • PHADDWQ
    Packed Horizontal Add Signed Word to Signed Quadword
  • PHSUBBW
    Packed Horizontal Subtract Signed Byte to Signed Word
  • PHSUBDQ
    Packed Horizontal Subtract Signed Doubleword to Signed Quadword
  • PHSUBWD
    Packed Horizontal Subtract Signed Word to Signed Doubleword
  • PMACSDD
    Packed Multiply Accumulate Signed Doubleword to Signed Doubleword
  • PMACSDQH
    Packed Multiply Accumulate Signed High Doubleword to Signed Quadword
  • PMACSDQL
    Packed Multiply Accumulate Signed Low Doubleword to Signed Quadword
  • PMACSSDD
    Packed Multiply Accumulate Signed Doubleword to Signed Doubleword with Saturation
  • PMACSSDQH
    Packed Multiply Accumulate Signed High Doubleword to Signed Quadword with Saturation
  • PMACSSDQL
    Packed Multiply Accumulate Signed Low Doubleword to Signed Quadword with Saturation
  • PMACSSWD
    Packed Multiply Accumulate Signed Word to Signed Doubleword with Saturation
  • PMACSSWW
    Packed Multiply Accumulate Signed Word to Signed Word with Saturation
  • PMACSWD
    Packed Multiply Accumulate Signed Word to Signed Doubleword
  • PMACSWW
    Packed Multiply Accumulate Signed Word to Signed Word
  • PMADCSSWD
    Packed Multiply, Add and Accumulate Signed Word to Signed Doubleword with Saturation
  • PMADCSWD
    Packed Multiply Add and Accumulate Signed Word to Signed Doubleword
  • PPERM
    Packed Permute Bytes
  • PROTB
    Packed Rotate Bytes
  • PROTD
    Packed Rotate Doublewords
  • PROTQ
    Packed Rotate Quadwords
  • PROTW
    Packed Rotate Words
  • PSHAB
    Packed Shift Arithmetic Bytes
  • PSHAD
    Packed Shift Arithmetic Doublewords
  • PSHAQ
    Packed Shift Arithmetic Quadwords
  • PSHAW
    Packed Shift Arithmetic Words
  • PSHLB
    Packed Shift Logical Bytes
  • PSHLD
    Packed Shift Logical Doublewords
  • PSHLQ
    Packed Shift Logical Quadwords
  • PSHLW
    Packed Shift Logical Words
  • PTEST
    Predicate Test Register
  • ROUNDPD
    Round Packed Double-Precision Floating-Point
  • ROUNDPS
    Round Packed Single-Precision Floating-Point
  • ROUNDSD
    Round Scalar Double-Precision Floating-Point
  • ROUNDSS
    Round Scalar Single-Precision Floating-Point