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bookmark siteIntel Itanium 2 9000 series Dual-Core processor (Montecito)
Dual-Core processor based on Intel Itanium 2 Madison 9M processor.
Identification
Model name:
Itanium 2 9000 series Dual-Core.
Code name:
Montecito.
Family name:
Itanium Processor Family (IPF).
Supplier:
Intel.
Component class:
CPU.
Generation
Generation: Itanium 2.
Compatibility
Bi-endian memory access.
Virtualization Technology for Itanium (VT-i).
IA-32 compatibility mode: IA-32 System Environment.
16 bit Real Mode, 16 bit VM86, 16/32 bit Protected Mode, memory segmentation.
Multimedia instruction sets: MMX, SSE, SSE2.
PA-RISC supported through Aries emulator.
Extensible Firmware Interface (EFI).
System Abstraction Layer (SAL).
Processor Abstraction Layer (PAL).
Cache
On-die L1 cache (Harvard architecture):
- (2x) 16 kbyte instruction cache,
- (2x) 16 kbyte data cache.
On-die, unified L2 cache: (2x) 256 kbyte.
On-die, unified, asynchronous L3 cache: shared, up to 2x 12 = 24 Mbyte.
Architecture
Virtual address space: 64 bit, no segmentation.
Multiple Address Space (MAS): each process has its own unique Virtual Region (flat linear address space).
8 61 bit Virtual Regions, 224 Virtual Address Spaces of 261 bits.
4 kbyte - 4 Gbyte pages.
Physical address space: 63 bit.
Up to 50 bits supported in page tables.
Write Coalescing (WC): streams of non-cachable writes can be combined into a single bus write transaction.
WC Buffer (WCB): two-entry, 128 byte.
Enhanced Machine Check Architecture (EMCA): parity and ECC (Error-Correcting Code) on all major address and data busses.
50 bit address bus.
Physical addressing:
- 32 bit: 0-4 Gbyte,
- 36 bit: 4-64 Gbyte,
- 44 bit: 64 Gbyte - 16 Tbyte.
Page sizes: 4 kbyte - 4 Gbyte.
200/266 MHz DDR bus (McKinley bus, Scalability Port): 128 bit data.
Multi-processing
Hyper-Threading Technology (HTT): Temporal Multi-Threading (TMT).
SMP (Symmetric Multi-Processing): glueless up to four processors (max. 16 in IA-32 compatibility mode).
Processors must have identical cache sizes and clock speeds.
Multiplier
Multiplier: 2/12, 2/14, 3/16.
Power management
Power and performance management: P-states.
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Clock speed
| Clock speed | Model | Cache | Multiplier | Periphery | Power dissipation | Introduction | Cancellation |
|---|---|---|---|---|---|---|---|
| 266/1600 MHz | Intel Itanium 2 9010 1 CPU | 6 Mbyte L3 | 6 | max. 74 °C | 75 W TDP | July 2006 | July 2011 |
| 200/1400 MHz | Intel Itanium 2 9015 Dual-Core CPU | 12 Mbyte L3 | 7 | max. 76 °C | 104 W TDP | July 2006 | July 2011 |
| 266/1420 MHz | Intel Itanium 2 9020 Dual-Core CPU | 12 Mbyte L3 | 5.33 | max. 76 °C | 104 W TDP | July 2006 | July 2011 |
| 266/1600 MHz | Intel Itanium 2 9030 Dual-Core 2 CPU | 8 Mbyte L3 | 6 | max. 76 °C | 104 W TDP | July 2006 | July 2011 |
| 266/1600 MHz | Intel Itanium 2 9040 Dual-Core CPU | 18 Mbyte L3 | 6 | max. 76 °C | 104 W TDP | July 2006 | July 2011 |
| 266/1600 MHz | Intel Itanium 2 9050 Dual-Core CPU | 24 Mbyte L3 | 6 | max. 76 °C |
104 W |
July 2006 | July 2011 |
Physics
Manufacturing process: 90 nm.
High-speed transistors only where necessary, to lower dissipation.
Number of transistors: 1720 million:
- core logic: 2x 28.5 = 57 million,
- L1 and L2 caches: 106.5 million,
- 24 Mbyte L3 cache: 1550 million,
- bus logic and I/O: 6.7 million.
Die size: 27.72 x 21.5 = 596 mm2.
Packaging: PAC611.
Thermal management
Thermal management:
- Thermal Alert,
- Enhanced Thermal Management (ETM),
- Thermal Trip.
System management
System management: System Management Bus (SMBus).
Step level
Text:
Step levels: C1, C2.
S-Spec / Stepping code
| Code | Stepping | CPUID | Clock speed | Description |
|---|---|---|---|---|
| L98T | C1 | 0020000504 | 266/1600 MHz | 24 Mbyte L3 cache |
| L9DF | C1 | 0020000504 | 266/1600 MHz | 24 Mbyte L3 cache |
| L9DG | C1 | 0020000504 | 266/1600 MHz | 18 Mbyte L3 cache |
| L9DE | C1 | 0020000504 | 266/1420 MHz | 12 Mbyte L3 cache |
| L9BW | C1 | 0020000504 | 200/1400 MHz | 12 Mbyte L3 cache |
| L9DH | C1 | 0020000504 | 266/1600 MHz | 8 Mbyte L3 cache |
| L9DJ | C1 | 0020000504 | 266/1600 MHz | 6 Mbyte L3 cache |
| L9P7 | C2 | 0020000704 | 266/1600 MHz | 24 Mbyte L3 cache |
| Code | Stepping | CPUID | Clock speed | Description |
| L9PG | C2 | 0020000704 | 266/1600 MHz | 24 Mbyte L3 cache |
| L9P8 | C2 | 0020000704 | 266/1600 MHz | 18 Mbyte L3 cache |
| L9PB | C2 | 0020000704 | 266/1420 MHz | 12 Mbyte L3 cache |
| L9PC | C2 | 0020000704 | 200/1400 MHz | 12 Mbyte L3 cache |
| L9P9 | C2 | 0020000704 | 266/1600 MHz | 8 Mbyte L3 cache |
| L9PA | C2 | 0020000704 | 266/1600 MHz | 6 Mbyte L3 cache |
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