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Intel Itanium 2 DP LV processor (Deerfield)
Low voltage, DP version of Intel Itanium 2 Madison processor.
Identification
Model name:
Itanium 2 LV.
Code name:
Deerfield.
Family name:
Itanium Processor Family (IPF).
Supplier:
Intel.
Component class:
CPU.
Generation
Generation: Itanium 2.
Compatibility
Bi-endian memory access.
Processor virtualization.
IA-32 compatibility mode: IA-32 System Environment.
16 bit Real Mode, 16 bit VM86, 16/32 bit Protected Mode, memory segmentation.
Multimedia instruction sets: MMX, SSE.
PA-RISC supported through Aries emulator.
Extensible Firmware Interface (EFI).
System Abstraction Layer (SAL).
Processor Abstraction Layer (PAL).
Cache
On-die L1 cache (Harvard architecture):
- 16 kbyte instruction cache,
- 16 kbyte data cache.
On-die, unified L2 cache: 256 kbyte.
On-die, unified L3 cache: 1.5 Mbyte.
Architecture
Virtual address space: 64 bit, no segmentation.
Multiple Address Space (MAS): each process has its own unique Virtual Region (flat linear address space).
8 61 bit Virtual Regions, 224 Virtual Address Spaces of 261 bits.
4 kbyte - 4 Gbyte pages.
Physical address space: 63 bit.
Up to 50 bits supported in page tables.
Write Coalescing (WC): streams of non-cachable writes can be combined into a single bus write transaction.
WC Buffer (WCB): two-entry, 128 byte.
Enhanced Machine Check Architecture (EMCA): parity and ECC (Error-Correcting Code) on all major address and data busses.
50 bit address bus.
Physical addressing:
- 32 bit: 0-4 Gbyte,
- 36 bit: 4-64 Gbyte,
- 44 bit: 64 Gbyte - 16 Tbyte.
Page sizes: 4 kbyte - 4 Gbyte.
200 MHz DDR bus (McKinley bus, Scalability Port): 128 bit data.
Multi-processing
SMP (Symmetric Multi-Processing): glueless up to two processors only ("DP Optimized").
Multiplier
Multiplier: 2/10.
Power management
Power and performance management: P-states.
Clock speed
| Clock speed | Model | Cache | Multiplier | Periphery | Power dissipation | Introduction |
|---|---|---|---|---|---|---|
| 200/1000 MHz | Intel Itanium 2 1000 DP LV 1.5MB CPU | 1.5 Mbyte L3 | 5 | max. 93 °C | 62.0 W TDP | September 2003 |
Physics
Manufacturing process: 130 nm.
Number of transistors: 410 million.
Die size: 374 mm2.
Packaging: PAC611.
Thermal management
Thermal management:
- Thermal Alert,
- Enhanced Thermal Management (ETM),
- Thermal Trip.
System management
System management: System Management Bus (SMBus).
Step level
Text:
Step levels: B1.
S-Spec / Stepping code
| Code | Stepping | CPUID | Clock speed | Description |
|---|---|---|---|---|
| SL754 | B1 | 001F010504 | 200/1000 MHz | 1.5 Mbyte L3 cache |
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