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Intel Itanium 2 processor (McKinley)


Model name: Itanium 2.
Code name: McKinley.
Family name: Itanium Processor Family (IPF).
Supplier: Intel.
Component class: CPU.


Generation: Itanium 2.


Bi-endian memory access.

Processor virtualization.

IA-32 compatibility mode: IA-32 System Environment.
16 bit Real Mode, 16 bit VM86, 16/32 bit Protected Mode, memory segmentation.
Multimedia instruction sets: MMX, SSE.
Erratum: IA-32 CPUID instruction always reports L3 cache to be 3 Mbyte.

PA-RISC supported through Aries emulator.

Extensible Firmware Interface (EFI).
System Abstraction Layer (SAL).
Processor Abstraction Layer (PAL).


On-die L1 cache (Harvard architecture):

  • 16 kbyte instruction cache,
  • 16 kbyte data cache.

On-die, unified L2 cache: 256 kbyte.

On-die, unified L3 cache: up to 3 Mbyte.


Virtual address space: 64 bit, no segmentation.
Multiple Address Space (MAS): each process has its own unique Virtual Region (flat linear address space).
8 61 bit Virtual Regions, 224 Virtual Address Spaces of 261 bits.
4 kbyte - 4 Gbyte pages.

Physical address space: 63 bit.
Up to 50 bits supported in page tables.

Write Coalescing (WC): streams of non-cachable writes can be combined into a single bus write transaction.
WC Buffer (WCB): two-entry, 128 byte.

Enhanced Machine Check Architecture (EMCA): parity and ECC (Error-Correcting Code) on all major address and data busses.

50 bit address bus.
Physical addressing:

  • 32 bit: 0-4 Gbyte,
  • 36 bit: 4-64 Gbyte,
  • 44 bit: 64 Gbyte - 16 Tbyte.
Virtual addressing: 54 bit.
Page sizes: 4 kbyte - 4 Gbyte.

200 MHz DDR bus (McKinley bus, Scalability Port): 128 bit data.


SMP (Symmetric Multi-Processing): glueless up to four processors (max. 16 in IA-32 compatibility mode).
Processors must have identical cache sizes and clock speeds.


Multiplier: 2/9, 2/10.

Power management

Power and performance management: P-states.

Clock speed

Clock speed Model Cache Multiplier Performance Periphery Power dissipation Introduction
200/900 MHz Intel Itanium 2 900 1.5MB CPU 1.5 Mbyte L3 4.5   5-85 °C 90.0 W TDP July 2002
200/1000 MHz Intel Itanium 2 1000 3MB CPU 3 Mbyte L3 5 SPECint2000 810,
SPECfp2000 1356
5-85 °C 100.0 W TDP July 2002


Voltage: 1.5 V.
Power dissipation: 130 W TDP.

Manufacturing process: 180 nm, 6 layer aluminium.

Number of transistors: 221 million.

Die size: 21.6 x 19.5 = 421 mm2.

Packaging: PAC611.

Thermal management

Thermal management:

  • Thermal Alert,
  • Enhanced Thermal Management (ETM),
  • Thermal Trip.

System management

System management: System Management Bus (SMBus).

Step level


Step levels: B3.

S-Spec / Stepping code

Code Stepping CPUID Clock speed Description
SL67U B3 001F000704 200/1000 MHz 1.5 Mbyte L3 cache
SL67V B3 001F000704 200/1000 MHz 3 Mbyte L3 cache
SL67W B3 001F000704 200/900 MHz 1.5 Mbyte L3 cache
SL6P5 B3 001F000704 200/1000 MHz 1.5 Mbyte L3 cache
SL6P7 B3 001F000704 200/1000 MHz 3 Mbyte L3 cache
SL6P6 B3 001F000704 200/900 MHz 1.5 Mbyte L3 cache

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