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More Details on Intel's Tukwila Itanium Processor

First silicon shown at IDF

October 17, 2007 - At IDF, Intel showed a wafer carrying dies of its next-generation Itanium processor. According to The Inquirer, the Tukwila dies are twice as big as the Nehalem dies, which are twice as big as the Penryn dies.

The Tukwila processor will be a Quad-Core CPU, based on an improved version of the current Itanium 2 generation. Each core will be able to run two threads.

Interconnects

The Tukwila processor (Itanium 3?) will feature an integrated FB-DIMM memory controller, enabling memory local to small group of processors as well as non-uniform memory links between as many as 128 processors over a more widely distributed system. The Double Device Data Correction (DDDC, memory RAS) enables data recovery for two sequential DRAM devices.

Up to six QuickPath channels (QPI: QuickPath Interconnect; CSI: Coherent Scalable Interconnect / Common System Interconnect/Interface) replace the current Front-Side Bus (FSB). Compare AMD's HyperTransport bus. Itanium's CSI will not be plug-and-play compatible with Xeon's CSI (Nehalem, from 2008), but the two processors will have a common chipset.

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